The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for testing integrated circuits and more specifically to isolating failing latches within an integrated circuit using a logic built-in self-test (LBIST).
Testing of integrated circuit devices is an important factor in ensuring proper functionality of the integrated circuit devices as well as for determining the functional capabilities of the integrated circuit devices for categorization purposes. As integrated circuit devices have become more complex, in an effort to reduce the complexity and cost of the external testing equipment, testing of the integrated circuit devices has moved from the exclusive use of external testing equipment to greater dependence on built-in self-test (BIST) circuitry provided on the integrated circuit device itself. Such BIST circuitry may be used to test the functional logic of the integrated circuit device (LBIST), arrays of the integrated circuit device (ABIST), or the like.
Typically, with LBIST circuitry provided on the integrated circuit device, a test pattern generator generates a test pattern that is applied to the functional logic of the integrated circuit device, or circuit under test (CUT), which in turn outputs a response to a response analyzer that generates a signature based on the analyzed response. With LBIST, all of the logic on the integrated circuit device is tested using a large number of test patterns to ensure high test coverage. The resultant data generated by the logic of the integrated circuit device is captured in “strings” of output latches of the integrated circuit device. After all of the scheduled tests have been completed, the final result is compared to a final result generated by a simulation or an integrated circuit device that is known to operate properly. Based upon this comparison, the integrated circuit device under test may be identified as working properly or incorrectly. However, current LBIST circuitry only identifies whether the entire integrated circuit device under test is defective or not.